\doxysection{RCC\+\_\+\+PLLInit\+Type\+Def Struct Reference}
\hypertarget{struct_r_c_c___p_l_l_init_type_def}{}\label{struct_r_c_c___p_l_l_init_type_def}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}


RCC PLL configuration structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+rcc.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a6cbaf84f6566af15e6e4f97a339d5759}{PLLState}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a72806832a179af8756b9330de7f7c6a8}{PLLSource}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_af8ae37696b35fd358c1ec1f6391158a4}{PLLM}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a2482608639ebfffc51a41135c979369b}{PLLN}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a4ecedf3ef401fa564aa636824fc3ded0}{PLLP}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a2b69dfec4b8ab52d649a71d141892691}{PLLQ}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a41208d1f84fc268f14fed2c825d07fbc}{PLLR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_af20c4077f568f28ef35457a6a5d1cf99}{PLLRGE}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a3f9f8f621863b38c1fca3328280f9d1f}{PLLVCOSEL}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l_init_type_def_a05da50ae75159764976992531612ee90}{PLLFRACN}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
RCC PLL configuration structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_r_c_c___p_l_l_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_c_c___p_l_l_init_type_def_a05da50ae75159764976992531612ee90}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLFRACN@{PLLFRACN}}
\index{PLLFRACN@{PLLFRACN}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLFRACN}{PLLFRACN}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a05da50ae75159764976992531612ee90} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLFRACN}

PLLFRACN\+: Specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191 \Hypertarget{struct_r_c_c___p_l_l_init_type_def_af8ae37696b35fd358c1ec1f6391158a4}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLM@{PLLM}}
\index{PLLM@{PLLM}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLM}{PLLM}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_af8ae37696b35fd358c1ec1f6391158a4} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLM}

PLLM\+: Division factor for PLL VCO input clock. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 63 \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a2482608639ebfffc51a41135c979369b}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLN@{PLLN}}
\index{PLLN@{PLLN}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLN}{PLLN}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a2482608639ebfffc51a41135c979369b} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLN}

PLLN\+: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min\+\_\+\+Data = 4 and Max\+\_\+\+Data = 512 or between Min\+\_\+\+Data = 8 and Max\+\_\+\+Data = 420(\texorpdfstring{$\ast$}{*}) (\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a4ecedf3ef401fa564aa636824fc3ded0}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLP@{PLLP}}
\index{PLLP@{PLLP}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLP}{PLLP}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a4ecedf3ef401fa564aa636824fc3ded0} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLP}

PLLP\+: Division factor for system clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 128 odd division factors are not allowed \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a2b69dfec4b8ab52d649a71d141892691}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLQ@{PLLQ}}
\index{PLLQ@{PLLQ}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLQ}{PLLQ}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a2b69dfec4b8ab52d649a71d141892691} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLQ}

PLLQ\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a41208d1f84fc268f14fed2c825d07fbc}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLR@{PLLR}}
\index{PLLR@{PLLR}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLR}{PLLR}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a41208d1f84fc268f14fed2c825d07fbc} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLR}

PLLR\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l_init_type_def_af20c4077f568f28ef35457a6a5d1cf99}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLRGE@{PLLRGE}}
\index{PLLRGE@{PLLRGE}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLRGE}{PLLRGE}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_af20c4077f568f28ef35457a6a5d1cf99} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLRGE}

PLLRGE\+: PLL1 clock Input range This parameter must be a value of \doxylink{group___r_c_c___p_l_l1___v_c_i___range}{RCC PLL1 VCI Range} \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a72806832a179af8756b9330de7f7c6a8}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLSource@{PLLSource}}
\index{PLLSource@{PLLSource}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLSource}{PLLSource}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a72806832a179af8756b9330de7f7c6a8} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLSource}

RCC\+\_\+\+PLLSource\+: PLL entry clock source. This parameter must be a value of \doxylink{group___r_c_c___p_l_l___clock___source}{RCC PLL Clock Source} \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a6cbaf84f6566af15e6e4f97a339d5759}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLState@{PLLState}}
\index{PLLState@{PLLState}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLState}{PLLState}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a6cbaf84f6566af15e6e4f97a339d5759} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLState}

The new state of the PLL. This parameter can be a value of \doxylink{group___r_c_c___p_l_l___config}{RCC PLL Config} \Hypertarget{struct_r_c_c___p_l_l_init_type_def_a3f9f8f621863b38c1fca3328280f9d1f}\index{RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}!PLLVCOSEL@{PLLVCOSEL}}
\index{PLLVCOSEL@{PLLVCOSEL}!RCC\_PLLInitTypeDef@{RCC\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLVCOSEL}{PLLVCOSEL}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l_init_type_def_a3f9f8f621863b38c1fca3328280f9d1f} 
uint32\+\_\+t RCC\+\_\+\+PLLInit\+Type\+Def\+::\+PLLVCOSEL}

PLLVCOSEL\+: PLL1 clock Output range This parameter must be a value of \doxylink{group___r_c_c___p_l_l1___v_c_o___range}{RCC PLL1 VCO Range} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__rcc_8h}{stm32h7xx\+\_\+hal\+\_\+rcc.\+h}}\end{DoxyCompactItemize}
